1. Field
An aspect of the invention relates to a reflow process evaluation device and a reflow process evaluation method for supporting and evaluating the design of a reflow process for mounting an LSI package.
2. Description of the Related Art
An LSI chip and a substrate are joined by soldering through a reflow method to treat the smaller size and higher density of the LSI chip, thereby manufacturing the LSI package.
FIG. 8 shows a perspective view and a side view of the LSI chip and the substrate, and FIG. 9 shows an enlarged view of a wiring layer position and a wiring layer of the LSI chip. Owing to a thermal stress when soldering the LSI chip with the substrate, a joined solder portion on the side of the wiring layer of the LSI chip may be stripped (e.g., near the wiring layer in the enlarged view of FIG. 8), resulting in a significant problem in securing the reliability of the product.
As its countermeasure, there is a method for making the evaluation through a thermal stress simulation for evaluating the reliability against the stripping. In this evaluation method, the maximum stress on the overall chip is an evaluation index.
As shown in the prior art associated with this technology, a system for predicting the life of a solder joint more rapidly has been disclosed (e.g., patent document 1). Also, as shown in the prior art, an enhancement system capable of evaluating the optimal solder material and the component electrode constitution has been disclosed (e.g., patent document 2). Further, a failure occurrence prediction method and a highly reliable life estimation method for BGA subjected to a cold shock have been disclosed (e.g., patent document 3).    [Patent document 1] Japanese Laid-open Patent Publication No. 2006-313127    [Patent document 2] Japanese Laid-open Patent Publication No. 2001-358460    [Patent document 3] Japanese Laid-open Patent Publication No. 2001-298107